1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Related Art
In recent years, there is known an FBC memory device as a semiconductor memory device expected to replace a 1T (Transistor)-1C (Capacitor) DRAM. The FBC memory device is configured so that FETs (Field Effect Transistors) each including a floating body (hereinafter, also “body”) are formed on an SOI (Silicon On Insulator) substrate, and so that data “1” or “0” is stored in each FET according to the number of majority carriers accumulated in the body of the FET.
Conventionally, capacitive coupling between the body and the substrate (fixed potential) is set strong so as to increase a signal difference (threshold voltage difference between the data “0” and “1”) of the FBC memory device. As one of methods of setting the capacitive coupling strong, a buried insulating film (BOX layer) of the SOI substrate is made thin. However, if the BOX layer is thin, a BOX layer under logic transistors loaded in mixture with the FBCs is made thin. Due to this, a capacity of a source or a drain of each of the logic transistors increases, disadvantageously resulting in decelerating operation performed by the logic transistor. Besides, the SOI substrate including the thin BOX layer is expensive. Considering these disadvantages, a technique for adopting FinFETs as FBCs is disclosed (T. Tanaka et al., “Scalability Study of a Capacitorless 1T-DRAM:From Single-gate PD-SOI to Double-gate FinDRAM”, IEDM Tech. Dig., pp. 919-922, December 2004 (hereinafter, “Non-patent document 1”)). However, if the FinFETs disclosed in the Non-patent document 1 are adopted, a memory cell array is disadvantageously made large in size.